Semiconductor devices, such as diodes, transistors, and integrated circuits are found everywhere in modern society. These devices are used in automobiles, cell phones, computers, televisions, satellites, and many other products. The semiconductor market has grown at a staggering pace over the years with improvements in performance and reduction in cost measured in orders of magnitude. This drastic improvement in semiconductor technology is due to the skill and technology advances in the ability to miniaturize devices so that more complicated devices can occupy smaller footprints on a wafer. The technology for the manufacture of semiconductors, specifically silicon devices, has matured into a reproducible and reliable manufacturing process. However, the manufacturing process is not perfect and wafers are still created that contain defects. Some of these defects prevent the full area of the wafer from being used as any device located over such a defect causes the device to fail or otherwise become inoperable. When an imperfection exists on a wafer, it is advantageous to know the location and level of imperfection so that the area sufficient for placing a device on a wafer can be known. Further, by performing the automatic mapping of defects during the manufacturing process, the growth parameters can be advantageously modified for improving crystal quality in subsequent wafer growth. Once the wafers are manufactured, the invention can assist with insuring quality control by measuring defects in specific production runs.
Referring now to a specific example, silicon carbide (SiC) wafers can be used for manufacturing high-frequency, high-powered, or high-temperature operating conditions for devices. Some of the advantages of SiC devices are that they have lower power dissipation, lower current leakage, and higher operational temperatures. In creating SiC devices, a SiC wafer is used as a foundation for the device. Unfortunately, SiC wafers contain defects, including dislocations such as threading edge, screw, and basal plane dislocations, and stacking faults. Specifically, micropipes are small tubular voids in the wafer that are generally oriented normal to the polished surface. The existence of micropipes and screw dislocations in the wafer, especially in high densities, prevents the use of large device areas for more powerful and complex devices. In fact, micropipes and screw dislocations have been identified as the main obstacle for commercializing large-area power devices. Micropipes lead to premature reverse breakdown in the SiC p-n junction and clearly adversely affect the electrical performance of the SiC device. The ability to detect the existence and physical location of the micropipes and screw dislocations on a wafer allows device manufacturers to determine the physical areas of the wafer where devices can be placed so that such defects will not degrade or destroy the functionality of the device.
Previously, methods for determining the number and location of micropipes in SiC wafers include KOH etching and transmission electron microscope (TEM). However, both are destructive methods resulting in a non-usable SiC wafer and not well suited for production line testing. While other methods exist, they require expensive equipment or special facilities. For example, synchrotron white-beam x-ray topography (SWBXT) requires a synchrotron light source that is available in only a few research facilities in the world. Other methods, such as atomic force microscopy (AFM), scanning electron microscopy SEM, and optical microscopy, while detecting micropipes, cannot detect closed-core screw dislocations in a non-destructive fashion. More specifically, it is advantageous to delineate and locate defects of the epitaxial films or layers. It is known that threading defects, such as micropipes, threading edge and screw dislocations, and grain boundaries, originating in the SiC or other substrate, penetrate the device structure during epitaxial growth and cause device failure or other inoperability. Further, process induced morphological defects can be caused by processes such as cutting, polishing, and preparing a wafer for growth.
Previously, there has not been an effective method or system to characterize the crystallographic defects and resulting morphological defects in the epilayer. Further, there has not been previously an effective method or system to determining threading defects, their propagation, or their correlation with growth pits of the epilayer, with or without the epilayer present.
Therefore, the development of a non-destructive, inexpensive, and rapid detection system and method for determining defects in semiconductors is a problem to which much attention should be directed.
Accordingly, it is an object of this invention to provide for an inexpensive, rapid, non-destructive system and method for determining defects in wafers.
It is another object of this invention to provide for an inexpensive non-destructive system and method for determining defects in wafers, with or without an epilayer.
It is another object of this invention to provide for an inexpensive non-destructive system and method for investigating threading defect propagation.
It is another object of this invention to provide for an inexpensive non-destructive system and method for investigating the relationship between wafer defects and device performance.